Hello, I'm
I build across the full stack of computing: from bare-metal assembly and FPGA circuit design to data pipelines and AI applications. Currently pursuing my master's in Computer Engineering on an accelerated 3+2 pathway.I bring hardware intuition, software depth, creativity, management and deterimation to every project.
Who I Am
I recently earned my Bachelor's in Computer Science and am currently in my second year of a Master's in Computer Engineering. My work spans both worlds; I've designed circuits in the lab, programmed in assembly, built databases, and created data visualizations. I also have experience with multiple developer tools, including Quartus, DB Gates, Oracle, GitHub, Cloud Shell, Tableau, Arduino, Cisco Packet Tracer, Notepad++, ModelSim, Google Colab, Nios II, IntelliJ, MATLAB, Dr. Racket, and more. Languages I have studied and applied over years of coursework and projects include C++, Assembly, Java, Python, SQL, and JavaScript. I have also completed an Introduction to Software Engineering course, where I gained hands-on knowledge of Agile, Scrum, and Extreme Programming (XP) methodologies. Beyond the technical curriculum, this course shaped me into a stronger collaborator, contributor, and problem-solver; reinforcing that great software is built by great teams, not just great code.
I'm actively seeking a high-impact internship or full-time role where I can contribute immediately while growing toward the engineer I'm becoming.
What I Do
FPGA design, circuit analysis, and low-level systems programming — a rare combination for a CS grad.
Object-oriented programming, algorithms, networking, and database systems across multiple languages and environments.
Turning raw data into insight — visualization, database building, and applied AI for engineering problems.
Environments & Tools
What I've Built
A fully playable Solitaire card game written entirely in x86 Assembly (MASM syntax) with no high-level language abstractions. Built as a team project in Visual Studio, it manages 13 stacks through raw push/pop operations and manual memory addressing, with every card encoded as a 32-bit hex value I designed from scratch. My contributions include the ANSI color rendering for suits in the console, the core put/take stack procedures the team built on, input validation logic, and the win condition detection across all four suit stacks. The project spans over 800 lines of hand-written assembly debugged entirely through Visual Studio's register and memory watch windows.
View Project
This 13-slide final presentation explores how linear algebra underpins Natural Language Processing. It covers NLP fundamentals (tokenization, embeddings, part-of-speech tagging), then dives into how vectors and matrices represent words and documents. Key topics include word embeddings, cosine similarity, Document-Term matrices, and Term-Term Co-occurrence matrices. The centerpiece is a deep dive into Hidden Markov Models (HMM):showing how transition/emission probability matrices power sequence analysis, with a worked example computing part-of-speech probabilities for the sentence "Bob ate the fruit." The conclusion ties it together: linear algebra is the mathematical backbone that makes modern NLP possible.
View Project
Built for ECE 215L at the University of Dayton, this FPGA-based reflex timer measures a user's reaction time to 0.01-second precision using the DE10-Lite board's 50 MHz clock. I designed a 4-state finite state machine in Verilog: Default, Lobby, Go, and Finish; that handles the full game flow: a button press triggers a 3-second delay, the LED flashes on, the timer counts, and a second press stops it. The result displays in SS.CC format across four 7-segment displays. I also built an advanced version that connects the FPGA to an Arduino Nano via 11 parallel GPIO pins, transmitting the reaction time as raw binary signals. The Arduino reconstructs the time and responds with a servo motor and buzzer, a fast reaction gets a full 180° sweep and high-pitched beep, medium gets a partial spin and softer tone, and slow gets barely a movement. The entire timing system, button edge detection, display decoder, and Arduino interface were coded and wired by me.
View Project
For ECE 303L Signals and Systems Lab at the University of Dayton, I designed and physically built 2nd-order and 4th-order Butterworth low-pass filters using the Sallen-Key topology with op-amps, resistors, and capacitors. I selected component values using MATLAB, assembled the circuits on a breadboard, and measured the magnitude frequency response using an oscilloscope and waveform generator across a range of frequencies from 200 Hz to 2000 Hz. I then used MATLAB to plot both the empirical and theoretical responses side by side, verifying how closely the physical circuit matched the mathematical model. The experiment also required deriving the Sallen-Key transfer function by hand using KCL and Laplace domain node-voltage analysis. Comparing the 2nd and 4th-order filters showed clearly how cascading stages sharpens the transition from passband to stopband a core concept in analog filter design.
View Project
For ECE 509: Analysis of Linear Systems at the University of Dayton, I completed a comprehensive project analyzing a state-space linear system through three approaches: hand derivations, MATLAB simulation, and Simulink modeling. Starting from a given state-space system, I derived the transfer function using g(s) = C(sI − A)⁻¹B + D, then solved for the zero-state response using Laplace transforms and partial fractions, and the zero-input response using eigenvalues and initial conditions. I combined both to find the total system response and plotted all three in MATLAB. Beyond the math, I verified every result in Simulink by building transfer function block models and state-space block models from scratch, confirming that the hand derivations and simulations matched exactly. I also analyzed the system's stability using eigenvalues (λ₁ = −2, λ₂ = −4), proved it was both controllable and observable.
View Project
Built entirely independently for an Advanced Data Structures course, this C++ project implements a templated Bag Abstract Data Type from scratch using object-oriented design. I designed a pure virtual abstract interface class that defines the full contract for all bag operations, then implemented it with an array-based Bag class using C++ templates so it works with any data type. The core of the project is three set operations I wrote from the ground up: union, which merges all items from both bags while preserving every duplicate; intersection, which finds shared elements and adds only the minimum frequency of each so if "Pens" appears twice in Bag1 and three times in Bag2 the result gets exactly two; and symmetric difference, which collects items that exist in one bag but not the other. A menu-driven client program lets the user choose which operation to run across two pre-filled string bags, using dynamic_cast to access the set operation methods through the abstract interface pointer.
View Project
A three-part interactive Tableau dashboard analyzing what factors influence Doctoral program offerings across U.S. universities. Using real institutional data, I built visual izations exploring enrollment size, religious affiliation, and public vs. private status; finding that institution size and geography are the strongest predictors, while religious affiliation has minimal impact. The project involved calculated fields, enrollment size grouping, color-coded degree type filters, and tooltip-driven interactivity across a scatter plot, grouped bar chart, and regional bar chart.
View Project
A two-phase school network design project built entirely in Cisco Packet Tracer. Starting from a 10.0.0.0/24 address space, I hand-calculated and configured subnets for 4 classrooms, an admin office, staff room, and server room; using /27, /28, and /29 subnet masks to minimize wasted IPs. I set up DHCP pools for all classroom PCs, assigned static IPs to admin and staff devices, and implemented ACL-based access control to block classroom traffic from reaching the admin subnet. In Phase 2, I expanded the network with WPA2-secured Wi-Fi (School and Guest networks), email, file, and print servers with role-specific ACL restrictions, SSH remote management, and guest network isolation, all configured using Cisco IOS commands.
View Project
Designed and implemented Booth's Algorithm for signed binary multiplication in VHDL for a Cyclone IV E FPGA (DE2 board). The design accepts two 8-bit signed inputs and produces a 16-bit product using three internal registers (A_reg, S_reg, P_reg) that shift and accumulate over N clock cycles based on bit-pair analysis. I wrote the full behavioral VHDL module and a testbench that reads test vectors from a CSV input file, simulated waveforms over 500ns in ModelSim with all tests passing, and compiled successfully in Quartus Prime using only 56 logic elements, under 1% of the available FPGA resources.
Watch VideoGet In Touch
Open to internships, research roles, and full-time opportunities. Let's connect.